IC manufacturing typically involves the sequential formation of multiple layers to form a single integrated device. The materials for each layer are chosen either because their properties allow them to inherently meet the required performance criteria for the IC device, or because their properties can be altered through the manufacturing process so that they meet those criteria. One type of material used to form a layer within an IC device is a dielectric.
Dielectric materials are electrical insulators, used to substantially electrically isolate conductive layers or features within the IC. The ratio of the amount of electrostatic energy that can be stored by a capacitor using a given dielectric material, as compared to the same capacitor with a vacuum as its dielectric, is defined as its ‘relative dielectric constant’ and is expressed as that material's ‘k’ value. Low-k dielectric materials may be viewed as those with a dielectric constant (‘k’ value) below that of silicon dioxide; (for SiO2, k≈4.0-4.2).
As transistor gate widths have shrunken with each subsequent generation of IC development, reducing interconnect delay has now become as important as reducing transistor switching frequency for boosting IC operating speeds. Two of the primary contributors to interconnect delay are the resistance of the metal (traditionally aluminum) used for the circuit lines, and the capacitance of the dielectric (traditionally silicon dioxide; SiO2) used for the interlayer dielectric (ILD).
To improve speed within the circuit lines, copper, which has approximately 30% lower electrical resistance than aluminum, has replaced aluminum in many high performance IC devices. However, copper has the lowest resistivity of metals that can easily be incorporated into IC devices, making reduction of ILD dielectric constant critical for realizing further decreases in interconnect delay times.
Several approaches have been identified for producing low-k ILD materials. Two methods which have been used or are being actively researched involve introducing carbon into the SiO2 matrix (to make a carbon-doped silicon oxide, referred to as CDO, OSG, SiOCH or SiCOH), and making the ILD porous. These techniques lower the k-value; however, they also reduce the density and mechanical strength of the ILD material. As a result, these materials are easily damaged by stresses imparted to the ILD during subsequent IC device fabrication processing. Damage could include cracking through the ILD, or delamination, where the ILD layer separates from one or more adjacent layers in the IC device. Damage may arise from thermomechanical stress imparted to the ILD when the IC device is subjected to thermal cycling during manufacturing process and normal use, due to differing coefficients of thermal expansion (CTE) among the ILD and adjacent layers. The fragility of low-k ILD materials is an impediment to their inclusion in high-volume IC fabrication.